Curriculum Vitae

Phil Cayton

Principal Systems Architect | AI/HPC Infrastructure, GPU I/O, Storage & Fabrics | Open Standards | Vice Chair, NVMe Technical Workgroup

Porvoo, Finland | cayton_cayton@impliedspaces.com | linkedin.com/in/philcayton/ | Github: https://github.com/cayton

EXECUTIVE SUMMARY

Principal systems architect with 31 years at Intel leading high-performance compute, storage, fabric, and accelerator-I/O architecture. Led the architecture and development work that produced the original NVMe over Fabrics prototype and initial NVMe/RDMA host and target implementations. Experienced in translating workload requirements into scalable infrastructure acro ss GPU data movement, storage, RDMA fabrics, CXL/fabric-attached memory, and open standards. Known for bringing technical consensus to multi-vendor environments: aligning 100+ companies, standards bodies, universities, and government partners around interoperable AI/HPC infrastructure that can be deployed and managed at scale.

CORE EXPERTISE

SELECTED INDUSTRY LEADERSHIP

• Vice Chair, NVMe Technical Workgroup (2026-present); Strategic Coordinator & Acting Chair (2022-2026): Appointed by the NVM Express Board of Directors to help lead the Technical Workgroup agenda and technical decision -making across NVMe specifications and a global member ecosystem.

• NVM Express Board Member (2025-2026): Strategic liaison aligning global AI/HPC storage standards.

• OpenFabrics Alliance Vice Chair & Board Member (2020-2026): Led roadmaps for composable-infrastructure management.

• Ultra Ethernet Storage Workgroup Chair (2024-2026): Drove development of NVMe over Ultra Ethernet Transport and aligned storage requirements across 100+ member companies.

• NVMe Boot Task Group Chair (2021-2026): Architected the NVMe Boot specification and led the multi-company group that delivered an open-source solution for booting over NVMe/TCP.

PROFESSIONAL EXPERIENCE

Intel Datacenter and AI Group | Principal Engineer / Sr. Staff Engineer | 2020-2026

• Led industry and standards work across NVMe, UEC, OFA, and SNIA, including NVMe over Fabrics, NVMe over Ultra Ethernet Transport, NVMe Boot, GPU I/O acceleration, and interoperable management architectures for hyperscale, AI, cloud, and HPC infrastructure.

• Architected NVMe Scalable Resource Management commands and features for dynamically constructing, configuring, and provisioning exported NVM subsystems from underlying physical resources, enabling dynamic multi-tenant infrastructure and standards-based NVMe storage virtualization and migration.

• Wrote the NVMe interface architecture for SNIA Swordfish and partnered with Swordfish’s principal architect on the schema extending DMTF Redfish management to NVMe and NVMe-oF resources.

• Served as Intel’s datacenter GPU-storage expert and Distributed AI Ultra Ethernet communications lead; developed a vendor neutral GPU I/O architecture to reduce NVMe/RDMA bottlenecks for GPU-intensive AI workloads, including upstream-kernel collaboration and an open CUDA-file implementation.

• Architected an Open Fabrics Management Framework for dynamic configuration, allocation, and provisioning across AI/HPC clusters; developed architectures and APIs spanning CXL/fabric-attached memory, burst buffers, and Flux integration. • Helped found the xIO industry SIG with NVIDIA, Intel, Meta, and Google to explore unified open -source storage stacks optimized across software and hardware platforms.

Intel Technical Computing Group | Staff Engineer / Senior Staff Engineer | 2012-2020 • Led the architecture and development work that produced the original NVMe over Fabrics prototype and initial NVMe/RDMA host and target implementations. Defined the transport-agnostic architecture and fabric interface approach that enabled NVMe semantics across high-performance transports.

• Steered the industry toward standards-based, scalable storage solutions; influenced specifications supporting increased scalability and manageability, including 3D XPoint / Optane use at scale.

• Optimized Xeon Phi RDMA access through OFED and contributed upstream kernel patches enabling low -latency transactions for high-density compute nodes.

Intel Energy Efficient Platform Labs | Senior Engineer | 2004-2012

• Led Intel/Nokia R&D (mobile augmented reality, wireless LAN clock control, RF mitigation, multi-radio performance optimization).

• Led university and public-sector research initiatives, including a $210K Intel/Arizona State University datacenter energy-efficiency project; managed proposals, budget, schedule, team, and demonstrations.

• Developed network acceleration and I/O technologies that delivered 3.5x gains over TCP socket connections and data transfer s.

SELECTED TECHNICAL LEADERSHIP AND PUBLICATIONS

• Speaker and panel leader at SC, FMS, DMTF, UEC, SNIA, and OFA events.

• Lead author of SNIA Swordfish and NVMe-oF Mapping Guide; author of NVMe 2.0 Enabling Efficient Boot over NVMe.

• Full catalog of 30+ talks, webinars, and publications available on request.

PATENTS

• 27 granted patents in high-performance I/O, disaggregated storage, and HPC fabrics.

EDUCATION

• MS, Computer Engineering, Oregon Health & Science University, 2002

• BS, Computer Science, Oregon State University, 1996

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