Curriculum Vitae

Phil Cayton

Principal Systems Architect | AI/HPC Infrastructure | Storage, Fabrics, GPU I/O & Open Standards

Email: cayton_cayton@impliedspaces.com | LinkedIn: www.linkedin.com/in/philcayton/

Location: Relocating to Finland (EET) | Eligible for Finland's 2-week Fast-Track Specialist Visa upon offer.

EXECUTIVE SUMMARY

Principal-level Systems Architect with 30+ years of experience engineering the foundational infrastructure, silicon interfaces, and open standards that power large-scale AI and High-Performance Computing (HPC) environments. Internationally recognized co-architect of NVMe-over-Fabrics (NVMe-oF). Expert at eliminating data movement bottlenecks to maximize GPU cluster utilization. Proven track record driving technical consensus across 100+ global multi-vendor companies, universities, and government agencies to turn fragmented capabilities into scalable, production-ready infrastructure.

Strengths: turning fragmented hardware, software, ecosystem capabilities into cohesive, high-performance AI/HPC infrastructure.

KEY IMPACT AREAS

· AI System Efficiency: Architected systems that reduce storage and network bottlenecks, improving accelerator utilization during large-scale AI training and inference workloads.

· Global Ecosystem Leadership: Directed technical consensus and alignment across 100+ multi-vendor technology companies to deliver interoperable, scale-out AI/HPC infrastructure. Led

high-impact initiatives spanning universities, government agencies, standards bodies, and multinational enterprise partnerships including Intel/Nokia and Intel/NVIDIA.

· Advanced Infrastructure Architecture: Designed fabric-attached storage, Composable Disaggregated Infrastructure, and low-latency transport architectures used as reference models

across the industry.

SELECTED INDUSTRY LEADERSHIP

· NVMe Consortium Board Member (2025–2026): Strategic liaison aligning global AI/HPC storage standards.

· NVMe Technical Working Group Strategic Coordinator & Acting Chair (2022-2026): Directed technical agenda across 11 NVMe specifications, aligning the roadmaps of 130+ global member companies to ensure the HPC/AI storage ecosystem remains interoperable and scalable.

· Open Fabrics Alliance Vice Chair & Board Member (2020 – 2026): Led strategic roadmaps for open-source high-performance fabrics & Composable Disaggregated Infrastructure ‘single pane of glass management’.

· Ultra Ethernet Storage Workgroup Chair (2024 – 2026): Drove development of the NVMe over UE Transport. Orchestrated interoperability for 100+ member companies to scale AI-native backend fabrics.

· NVMe Boot Task Group Chair (2021 – 2026): NVMe Boot spec Architect and leading the multi-company SIG that delivered an industry 1st open-source solution for booting over NVMe/TCP.

EXPERIENCE

2020 – August 2026: Principal Engineer / Sr. Staff Engineer | Intel Datacenter and AI Group

· Industry Influence and Leadership: Helped found the xIO industry SIG with NVIDIA, Intel, Meta, and Google to develop unified open-source storage stacks optimized across software and hardware platforms.

· Standards Leadership: Innovated and directed the evolution of NVMe, UEC, OFA, and SNIA standards including NVMe over Fabrics, SNIA Swordfish, NVMe over Ultra Ethernet Transport, Boot over NVMe, and GPU I/O Acceleration. Enabled new capabilities and unified scalable storage and fabric architectures for hyperscale, AI, cloud, and HPC infrastructure.

· AI Infrastructure Innovation: Served as Intel’s Datacenter GPU storage expert and Distributed AI Ultra Ethernet communications lead. Spearheaded development of a vendor-agnostic GPU I/O architecture to reduce NVMe/RDMA bottlenecks and improve accelerator utilization during large-scale AI workloads. Worked with upstream maintainers on kernel patches and developed an open CUDA-file implementation for GPU I/O acceleration.

· Composable Disaggregated Infrastructure R&D: Architected an Open Fabrics Management Framework for dynamic resource configuration, allocation, and provisioning across AI/HPC clusters. Developed architecture, APIs, NVMe & CXL fabric-attached memory interface concepts, burst-buffer architecture, and integration with Flux.

· Strategic Liaison: Represented Intel at executive levels within UEC, SNIA, and NVMe to align global standards with next-generation IPU and GPU silicon roadmaps.

2012 – 2020 Staff Engineer / Senior Staff Engineer | Intel Technical Computing Group

· High-speed Scale-out Storage Pioneer: Co-invented NVMe-over-Fabrics (NVMe-oF); led the cross-divisional team that delivered the first driver prototypes and fabric-agnostic interface libraries demonstrating NVMe/RDMA.

· Market Transformation: Steered the industry toward international award-winning standards-based solutions. Influenced specs to drive increased scalability and manageability. Drove 3DXPoint / Optane use at scale.

· High-Performance Networking Innovation: Optimized Xeon-Phi RDMA access via OFED, contributing upstream kernel patches that enabled low-latency transactions for high-density compute nodes.

2004-2012: Senior Engineer | Intel Energy Efficient Platform Labs

· International Transnational R&D Leads: Spearheaded joint Intel/Nokia engineering projects focusing on wireless LAN clock-control and RF mitigation, improving multi-radio system performance via adaptive clocking, RFI monitoring, frequency shifting.

· Coordinated cross-border collaborative research initiatives with FEMA, Oregon Health & Science University, and Manipal University: Led development of sensor-enabled mobile health systems for stroke/heart-attack detection, and emergency medical services field usage.

· University Research Lead: Intel and Arizona State University datacenter energy-efficiency project, developing research proposals, secured $210K in funding, managed budget, schedule, team, and demonstrations.

· Leader researcher developing network acceleration and I/O performance technologies, creating embedded acceleration stacks

yielding 3.5x gains over TCP socket connections and data transfers.

THOUGHT LEADERSHIP & INDUSTRY ENGAGEMENT

Recent Strategic Keynotes & Panels:

• UEC/SNIA/NVMe Joint Forum: Cross-consortium architecture presentations for NVMe/UE, UE kernel interface, SNIA Swordfish updates, GPU I/O acceleration. Coordinated the Technical Working Group.

• DMTF Annual Meeting: Delivered NVMe ‘State of the Union’ speech.

• Future of Memory and Storage (FMS) 2024: Delivered the "NVMe State of the Union," speech presenting the roadmap for the specification's evolution.

• Supercomputing (SC24): Led panels on "Industry Standards Accelerating AI/HPC" and "Composable Disaggregated Systems Management."

• Ultra Ethernet Consortium (UEC) Summit 2025: Orchestrated the Storage Birds of a Feather to align backend fabric requirements.

Recent Publications:

• Lead Author: SNIA Swordfish and NVMe-oF Mapping Guide (2024), an industry blueprint for hyperscale storage management.

• Author: NVMe 2.0: Enabling Efficient Boot over NVMe (2023), the standard for NVMe boot over TCP.

• Technical Evangelism: Prolific presenter (2016–2024) at the Open Fabrics Alliance & SNIA SDC Workshops on e.g., NVMe, Universal Fabric Management, Disaggregated Storage.

Full catalog of 30+ talks, webinars, and publications available upon request.

INTELLECTUAL PROPERTY & PATENTS

• Holder of 27 granted patents on high-performance I/O, disaggregated storage, and HPC fabrics.

NVMe-oF & Multi-Fabric Interoperability: Core architecture for routing independent NVMe I/O queues across distinct network addresses and enabling cross-fabric host-to-device communication.

Composable Disaggregated Infrastructure: Systems for disaggregating block storage controller stacks, management of virtual target resources, and dynamic distributed host discovery services.

Remote Initialization & Secure Access: Technical protocols for command validation by remote clients and foundational mechanics for initializing (booting) systems from remotely accessible storage devices.

Fabric Efficiency & Acceleration: Low-latency storage server flow control mechanisms, data replication architectures, and split-model drivers using push-push messaging over channel-based networks.

EDUCATION

MS Computer Engineering Oregon Health & Science University 2002

BS Computer Science Oregon State University 1996

TECHNICAL AREAS

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